1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device provided with test functions to test memory cells.
2. Description of the Related Art
Semiconductor memory devices such as DRAMs are subjected to inspections to check whether memory cells correctly function with regard to data storage capacity. Such inspections are conducted at a site of manufacturers before shipment of products. A test referred to as a disturb test activates a given word line, and writes data of either 0 or 1 in a memory cell. The word line is then deactivated, and surrounding word lines are switched back and forth between an active state and an inactive state. After this operation, the word line is activated again to check whether the data initially stored in the memory cell can be correctly read. This test can evaluate whether data of a given word line is affected when surrounding word lines are driven.
In conventional DRAMs, each bank is provided with one row-address-latch circuit, which latches a row address. When a given bank is activated, therefore, only one row address can be accessed in this bank. In this manner, conventional DRAMs allow only one word line to be activated at one time. Because of this limitation, the disturb test described above needs to repeat activation and deactivation with respect to each word line by successively selecting each word line.
Development of integrated-circuit technology makes it possible to manufacture DRAMs of a larger memory capacity, and such DRAMs have a larger number of word lines. As DRAMs have a larger capacity, therefore a time length required for testing a DRAM becomes undesirably lengthy. This raises an expectation for technology which can reduce the test time.
The test time can be reduced if a plurality of word lines can be simultaneously activated during a test mode. Such simultaneous activation can be readily achieved in the following manner.
A row-address decoder is provided inside a DRAM, and decodes a supplied row address to select one word line. Generally, such a row-address decoder receives complement signals as row address signals. That is, if a row address is represented by a set of three bits (A1, A2, A3), the row-address decoder receives signals representing A1, A2, and A3 as well as /A1, /A2, and /A3. NAND circuits are provided inside the row-address decoder for the decoding purposes, and each of the NAND circuits receives a corresponding selection of three bits chosen from A1, A2, A3, /A1, /A2, and /A3. For example, a given NAND circuit receives /A1, A2, and /A3. This NAND circuit outputs a LOW signal only when (A1, A2, A3) is (0, 1, 0). In this manner, each NAND circuit generates an output signal representing a corresponding row address.
When a row-address decoder with complement signals is used, it is relatively easy to activate a plurality of word lines simultaneously. This is achieved by forcing both A3 and /A3 to be HIGH, for example. In this case, two word lines corresponding to row address (1, 1, 0) and (1, 1, 1) are activated at one time. By the same token, forcing A2, /A2, A3, and /A3 to be HIGH results in activation of four word lines.
In this manner, a plurality of word lines can be simultaneously selected if complement signals are supplied to a row-address decoder.
A demand for chip-size reduction, however, requires some DRAM chips to be provided with a row-address decoder receiving only positive-logic signals. Namely, only A1, A2, and A3 are supplied without their complements /A1, /A2, and /A3. In such DRAMs, there is no straightforward method to activate a plurality of word lines at the same time.
As demand for a chip-size reduction becomes stronger, more DRAMs will be provided with a row-address decoder receiving only positive-logic signals. Against this background, we need to seek ways to achieve a simultaneous activation of a plurality of word lines for the purpose of reducing the test time.
Accordingly, there is a need for a semiconductor memory device which can reduce a test time of memory cells.